Structure of the Processor

Q1. Which register holds the address of the next instruction to be fetched?

Multiple Choice · 1 point

• · Program Counter (PC)
• · Memory Data Register (MDR)
• · Current Instruction Register (CIR)
• · Accumulator (ACC)

Q2. Which component of the CPU is responsible for carrying out arithmetic and logical operations?

Multiple Choice · 1 point

• · Control Unit (CU)
• · Arithmetic and Logic Unit (ALU)
• · Memory Address Register (MAR)
• · Cache

Q3. What is pipelining in the context of a CPU?

Multiple Choice · 1 point

• · Running multiple programs simultaneously on one core
• · Overlapping the fetch, decode and execute stages of multiple instructions
• · Storing frequently used instructions in cache
• · Dividing memory into segments for faster access

Q4. Which of the following correctly describes the Von Neumann architecture?

Multiple Choice · 1 point

• · Separate memory and buses for instructions and data
• · A single shared memory and bus for both instructions and data
• · Uses only ROM for program storage
• · Designed exclusively for parallel processing

Q5. Put the steps of the Fetch-Decode-Execute cycle in the correct order, including register operations.

Ordering · 2 points

• 1. Contents of PC copied to MAR
• 2. PC is incremented
• 3. Instruction fetched from memory address in MAR, placed in MDR
• 4. Contents of MDR copied to CIR
• 5. Instruction in CIR is decoded
• 6. Instruction is executed

Q6. State the purpose of the Memory Data Register (MDR).

Short Answer · 2 points

Q7. State three factors that affect the performance of a CPU.

Short Answer · 3 points

Q8. Describe the Fetch-Decode-Execute cycle, including the role of each register involved. You should refer to the PC, MAR, MDR, CIR and ACC.

Long Answer · 6 points

Q9. Explain how pipelining improves the efficiency of a CPU. In your answer, refer to what would happen without pipelining.

Long Answer · 4 points

Q10. Explain one difference between Von Neumann and Harvard architecture and state one application where Harvard architecture is preferred.

Short Answer · 3 points

Q11. Explain how increasing cache size can improve CPU performance, and state one limitation of this approach.

Short Answer · 3 points